The invention relates to a microprocessor system—for controlling safety-critical processes, with two central processing units integrated in a chip housing, two bus systems, at least one complete memory on the first bus system, test data in test data stores which are connected to data in the memory on the first bus system, where the test data store is smaller than the complete memory and the bus systems have comparison and/or driver components which allow the data interchange and/or comparison of data between the two bus systems.
DE 195 29 434 A1 (P 7959) discloses such a microprocessor system for safety-critical applications. For reasons of redundancy, this microprocessor system contains two homogeneous microprocessor cores (core redundancy) which execute the same program in clock synchronism and in parallel. The bus systems associated with the microprocessor systems are likewise provided in duplicate, but the memory is not of fully symmetrical design, for reasons of cost. It has been found that a high error recognition rate can be achieved if one of the two bus systems stores only test data in a test data store with relatively low storage capacity, said test data being explicitly associated with the complete data in the complete memory. So that both cores each have all the data available in redundant form, the complete data are continually compared with the test data using hardware generators. The hardware generators can either generate test data or can complement the test data for comparison using the complete data (data error correction).
It is an aim of the present invention to specify an alternative two-core microprocessor system which likewise comprises a complete memory and a test data store of relatively small size for storing redundancy information which is associated with the original data stored in the complete memory, and where the microprocessor system has an increased error recognition rate in comparison with corresponding two-core microprocessor systems.